Conventionally, hetero epitaxial growth is known as a method of epitaxially growing, on a single-crystal substrate, a material different from it. In hetero epitaxial growth, an epitaxial layer having a strained crystal lattice can be formed depending on the material and conditions of crystal growth. In an epitaxial layer having a strained crystal lattice, the atomic interval in the epitaxial layer increases due to tensile stress. Accordingly, the effective mass of carriers in the epitaxial layer decreases, and the carrier mobility can be increased.
As a technique using this fact, Japanese Patent Laid-Open No. 2000-286418 discloses a technique for increasing the carrier mobility by using a silicon layer (to be referred to as a “strained silicon layer” hereinafter) strained by an SiGe layer. In the strained Si technology, an Si layer is formed on an SiGe layer to strain the semiconductor layer to make the lattice constant of the semiconductor layer larger than that of the unstrained Si, thereby increasing the carrier mobility in a channel. When silicon is epitaxially grown on an SiGe layer, it grows complying with SiGe having a lattice constant larger than that of silicon (the lattice constant difference between Si and Ge is about 4%). Hence, strain of several % occurs (the strain amount changes depending on the amount of Ge contained in the SiGe layer).
On the Internet, an article titled “Two high-performance transistor techniques developed in front line of semiconductor field” is disclosed at http://www.mitsubishielectric.co.jp/news/2002/1217-b.ht ml with a dateline of Dec. 17, 2002. In this technique, tensile stress is applied to a silicon layer from its upper side to strain the crystal lattice of the silicon layer. For example, tensile stress is applied to a channel region from the side of a gate electrode formed above the channel region, thereby increasing the carrier mobility in the channel region.
However, in the technique of Japanese Patent Laid-Open No. 2000-286418, since the SiGe layer contains defects, it is difficult to form a strained silicon layer having high crystallinity. In the article disclosed on the Internet, after an unstrained silicon layer is formed, strain is introduced by a device structure formed on the silicon layer. In this case, the structure under the strained silicon layer is made of a material matched before the silicon layer is strained. For this reason, when strain is to be applied from the upper side of the silicon layer, a force which prevents the strain is generated in the layer under the silicon layer. Generally, when biaxial stress is applied to a silicon layer to strain it, a strain amount is generated in the plane of silicon in accordance withε=(1−ν)·σ/E  (Equation 1)where ε is the strain amount (no unit) in the plane of silicon, ν is the Poisson's ratio (no unit) of silicon crystal, σ is biaxial stress [GPa] applied in the plane of silicon, and E is the Young's modulus [GPa] of silicon crystal. Normally, to obtain 1% to 2% as the strain amount ε of silicon on SiGe when E=162 GPa, and ν=0.26, stress σ of 2.2 to 4.4 [GPa] is necessary. Hence, in a general Si-LSI (Large-Scale Integration) structure, not only the surface silicon layer but also an underlying portion must be strained. To do this, if stress is applied from the upper or side surface of the silicon layer, larger stress than the above value needs to be applied.
On the other hand, in manufacturing semiconductor devices, reduction of the element size progresses to implement high integration degree and high operation speed of semiconductor devices. However, along with the reduction of the element size, the carrier mobility decreases, and the leakage current increases. It is accordingly pointed out that the micropatterning technology should reach its physical limit in the future.
To cope with this problem, Japanese Patent Laid-Open No. 2000-286418 discloses a strained Si technology for increasing the carrier mobility of a transistor without depending on micropatterning. However, as described above, since an SiGe layer generally contains defects, it is difficult to form a strained silicon layer having high crystallinity.
“A folded-channel MOSFET for deep-sub-tenth micron era”, in IEDM Tech. Dig., 1998, pp. 1032–1034 discloses, as an epoch-making device structure next to the strained Si structure, a Fin FET developed by a group of Professor C. Hu et al in the University of California, Berkeley. In a conventional planar FET, the channel is controlled from the upper side by a gate electrode formed on silicon. In the Fin FET, a gate electrode is formed to sandwich a channel called a “Fin” on silicon so that the channel is controlled from both sides. With this structure, the increase in leakage current, which poses a problem in the conventional planar FET, can effectively be suppressed, and a finer device structure can be formed.
A Fin FET can easily be manufactured by using the current semiconductor device process. In addition, it is supposed that elements 400 times that in the prior art can be integrated on the chip. Hence, the Fin is regarded as a promising device structure of next generation.
In the Fin FET however, the channel is formed on a non-porous layer. If strain is to be applied from the upper side of the channel, a force which counteracts the strain is generated in the layer under the channel. Hence, the channel can hardly efficiently be strained.